Soc Physical Design Engineer

ppIn this role, you will implement physical design for Optical Network ASICs across cutting-edge nodes, focusing on power, performance, and area. You will work within a hardware/RTL team to translate designs into silicon and optimize flows for submicron processes. You’ll tackle floorplanning, placement, routing, and timing closure, shaping multi-project IP and design methodologies. The opportunity centers on delivering best-in-class silicon while learning the latest nodes and tools. You will contribute to a mission-driven environment that values automation and rigorous verification. /pulliFlexible and hybrid working schemes /liliParental leave (90 days) with return option /liliLife insurance for employees /liliWell-being programs for mental and physical health /liliParticipation in Nokia Employee Resource Groups (NERGs) /liliCareer development and coaching/mentoring /liliPerform floorplanning, place route, and power/clock distribution for blocks and full chips /liliExecute physical verification, IR/EM analysis, and timing closure at block and chip level /liliCollaborate with logic designers and hardware teams on feasibility studies and design trade-offs /liliEvaluate IP vendors, process nodes, and provide actionable recommendations /liliDevelop PD methodologies and automation scripts for steps from Synthesis to GDSII /liliConduct static timing analysis, create timing constraints, validate critical paths, and sign off timing /lili3+ years of experience in ASIC physical design flow and methodologies on 3/5/7nm nodes /liliSolid knowledge of RTL to GDSII and underlying IC design concepts /liliExperience with EDA tools: Fusion Compiler or Innovus, Primetime or equivalent, Calibre, Redhawk /liliScripting experience in TCL, Python or Perl /liliBachelor's degree or higher in Electrical/Electronics and Communication/VLSI/Microelectronics /liliStrong collaboration with cross-functional teams /liliteam collaboration /lilianalytical mindset /liliproblem solving /liliFloorplanning and placement/routing /li /ulpSoC Physical Design Engineer catania, sicilia, it /p /p #J-18808-Ljbffr