Senior Digital IC Design Engineer (RTL/Verilog)

pNXP Semiconductors in Italy (Catania) is seeking a Master’s-level IC design engineer to develop digital sub-circuits for SOCs using Verilog/SystemVerilog, RTL techniques and advanced verification. /ppYou will collaborate with analog, mixed-signal and software teams to optimize interfaces, perform design verification, participate in post-silicon validation and contribute to high-quality, testable ICs. /p #J-18808-Ljbffr