Risultati della ricerca: 3 offerte di lavoro
...and writing complex system-level test-benches in Verilog
Defining synthesis design constraints and resolving STA issues as well as gate-level simulation failures
Defining Clock/Reset domain crossing design constraints and evaluating violations using CDC/RDC tools...
...the creation of application and system related marketing materials
Train worldwide colleagues and distribution partners on your gate drivers and applications.
Requirements:
You strive for continuous development, take initiative, have excellent communication...
....
Job Description:
As Senior Test Development Engineer, you are involved in the entire project lifecycle and act as a quality gate that every EPC IC product must pass. We will be counting on your support to improve our test methodology continuously. You will be responsible...
Efficient Power Conversion
Pavia (PV)
3 giorni fa
