Design Verification Engineer SoC

The Chips-IT Foundation is seeking an experienced Verification Engineer to support the development and validation of advanced digital IPs and System-on-Chip (SoC) platforms. The role focuses on creating and maintaining verification environments using industry-standard methodologies (e.g., UVM), ensuring functional correctness of designs from specification to tape-out. The position also involves collaboration with design, architecture, and software teams to deliver reliable and high-quality silicon. The work can be carried out either in Pavia or in Bologna.

KEY RESPONSIBILITIES:

• Define and implement verification strategies at IP and SoC levels.
• Develop and maintain UVM-based verification environments, including testbenches and functional coverage.
• Design and execute test plans aligned with design specifications and requirements.
• Debug RTL and simulation issues using advanced tools and techniques.
• Integrate verification components and ensure complete test coverage.
• Contribute to regression infrastructure and manage automated test execution.
• Collaborate closely with RTL designers, DFT engineers, and physical implementation teams.
• Support post-silicon bring-up and validation activities as needed.