Senior Analog Layout Engineer
Jobtome
Experteer Overview
In this role you lead layout design for high-performance analog and mixed-signal ICs, driving floorplan and top-level integration while mentoring a layout team. You set up and debug LVS/DRC/ERC environments and collaborate with chip design leads on chip floorplans. You build critical analog blocks and ensure long-term reliability through design-for-quality practices. This position combines hands-on layout execution with leadership across multisite teams in a global environment.Retribuzione / Benefits
- Drive floorplan activities at IPs and SOC level
- Participate in power supply strategy and signal distribution
- Deliver analog layout blocks and top floorplan strategy
- Lead top-level integration using the Mixed Signal on Top flow
- Manage and schedule a layout team for SoC execution
- Run physical verifications (DRC/LVS/DFM) and parasitic extraction
- Participate in design reviews and create documentation for product integration
- Focus on design-for-quality with thorough verification and long-term reliability
- Identify root causes and solutions from 1st prototypes
- Provide technical training and write layout guidelines
- >
10 years of experience leading analog layout in complex ICs - Fluent in English
- Strong expertise in analog layouts, device physics and IC ESD protection
- Expert in layout tools Cadence Virtuoso (OA, PVS) and Mentor Graphics Calibre
- Ability to drive and collaborate with experienced people across profiles
- Experience managing multisite layout teams
- Experience delivering advanced floorplan strategies
- Experience in physical implementation of analog blocks at IP/SOC level
- Ability to train others and write guidelines for layout activities
- Experience with cross-functional teams and strong communication in a global environment
Offerta di lavoro pubblicata 6 giorni fa
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