Soc/Fpga Engineer

ppIn this role you drive the architecture, design and validation of ASICs for optical modules within Nokia's Optics Subsystems. You will work in an international SoC team to push higher transmission bandwidth while reducing power and size. You'll translate standards into framer designs, optimize RTL/verification flows, and collaborate across synthesis, physical design, firmware and systems teams. This is a hands-on, impact-focused opportunity to shape next-generation coherent transmission technologies. /pulliFlexible and hybrid working schemes /liliMaternity and paternity leave /liliLife insurance /liliNERGs and coaching/mentors /liliLearning and career growth opportunities /liliArchitect, specify, design and test ASICs for optical modules. /liliTranslate standards into framer architecture and optimize RTL/verification flows. /liliCollaborate with ASIC synthesis, implementation and physical design teams for handoff and optimization. /liliMentor junior engineers and contribute to team knowledge sharing. /liliCollaborate with systems, hardware, software and firmware teams across Nokia locations. /liliContribute to Framer development flow and integrate IPs, with a focus on efficiency and QoR. /liliMaster's degree or PhD in Electronic Engineering, Microelectronics, Telecommunication Engineering or equivalent /liliStrong knowledge of IEEE transmission standards (IEEE 802.3 focus) and Ethernet rates above 100G /liliProven experience in ASIC design and verification and access to toolchains (Synopsys, Mentor, Cadence) /liliProficiency in VHDL, Verilog, SystemVerilog; TCL and Python scripting /liliRTL design and verification experience with emphasis on high-performance, low-power ASICs /liliUVM verification experience is a plus /liliBasic knowledge of ECC theory and algorithms /liliBasic firmware development knowledge (C/C++, drivers, APIs); advanced skills a plus /liliGood written and spoken English; strong collaboration with international partners /liliCross-functional collaboration /liliMentoring and technical leadership /liliASIC design and verification workflows /li /ul /p #J-18808-Ljbffr