CAD & EDA Flow Engineer

h3About Fondazione Chips-IT /h3 pThe Foundation “Italian Center for the Design of Semiconductor Integrated Circuits,” also known as the Chips-IT Foundation, is a nonprofit research and technology organization under the supervision of the Ministries of Industry. The Foundation is Italy's first RTO (Research and Technology Organization) vertically focused on semiconductor research and stands as a center of excellence in frontier research on semiconductor design, as well as a pivotal center of the Italian semiconductor ecosystem and expertise. /p h3Missions Of The Foundation /h3 ul liPromote the design and development of integrated circuits /li liStrengthen the system of professional training in the field of microelectronics /li liEnsure the establishment of a network of universities, research centers and enterprises that fosters innovation and technology transfer in the field /li /ul h3CAD EDA Flow Engineer /h3 pWe are seeking a CAD EDA Flow Engineer to manage, optimize, and maintain our Electronic Design Automation (EDA) infrastructure. In this role, you will serve as the technical backbone for our RD teams, managing relationships with EDA vendors and foundries, and ensuring smooth PDK integration for advanced SoC design up to tape-out. /p pThe work can be carried out either in Pavia or in Bologna. /p h3Key Responsibilities /h3 ul liManage EDA tool procurement, licenses, and vendor relationships (Cadence, Synopsys, Siemens). /li liInstall, configure, and maintain Process Design Kits (PDKs) across all design workflows (digital, analog and RF). /li liAct as the primary technical liaison with foundries for PDK installation and maintenance, design rule checks (DRC/LVS), and issue resolution. /li liMaintain and optimize EDA toolchains for synthesis, simulation, verification, and physical implementation. Experience on emulation systems is a plus. /li liCreate and update internal trainings, technical documentation, scripts, and best practices for internal design teams. /li /ul h3Requisiti /h3 ul liMaster’s degree in Electrical/Computer Engineering or Microelectronics. /li liProven experience in EDA tool administration and PDK management (Cadence, Synopsys, Siemens). /li liGood knowledge of semiconductor fabrication flows and foundry interfaces. /li liFamiliarity with scripting languages (Tcl, Python, Bash) for design flow automation. /li liBasic understanding of HDL languages (Verilog, SystemVerilog, VHDL). /li liExperience with advanced process nodes is considered a strong plus. /li /ul h3Altre Informazioni /h3 pWHAT WE OFFER: /p ul liCompetitive compensation and contract type, to be negotiated based on qualifications and experience /li liPossibility to enter into a PhD conjugating your job with a research program that will grant you the PhD title. /li liLunch tickets /li liPrivate health care coverage depending on your role and contract /li liStructured growth path, with ongoing access to training and updates /li liNetworking opportunities with industry-leading professionals /li liInternational environment /li liHybrid work policy /li liTax deductions: Candidates from abroad, comprising Italian citizens, who have carried scientific research activity abroad and meet specific requirements, may be entitled to a taxable income deduction up to 90% for a period of 6 to 13 years /li /ul pIn conformità con le normative vigenti, il range retributivo lordo annuo previsto per questa posizione parte da Euro 60.000,00, con il fine di valutare candidature con diversi livelli di seniority; l'offerta finale sarà strettamente commisurata all'effettiva esperienza e alle competenze del candidato, e sarà integrata dai benefit aziendali previsti per il ruolo. /p #J-18808-Ljbffr