Senior Mixed Signal Verification Engineer

The Mixed Signal Verification Lead will ensure high‑quality designs that meet requirements, working closely with designers and systems engineers to create simulation test cases, models, checkers, and alike.

Responsibilities

• Work with global design teams to develop complex SOCs while maintaining a high level of quality.
• Define and execute a verification strategy for mixed‑signal designs and systems.
• Create verification plans and traceability of requirements to ensure complete coverage.
• Develop functional models of analog blocks using SystemVerilog for system‑level verification.
• Create AMS models of analog blocks and subsystems to verify electrical behavior of mixed‑signal systems.
• Run simulations and track coverage of verification plans.
• Ensure high‑quality tape‑outs and A0 silicon go to production.
• Provide post‑silicon debug support to identify and resolve silicon issues, improving product performance and reliability.

Qualifications

• Bachelor’s Degree in Electronic Engineering; Master’s degree preferred.
• 5+ years of production mixed‑signal verification experience.
• SystemVerilog modeling experience required.
• Experience with assertions, checkers, and similar digital verification techniques highly desirable.
• Ability to visually inspect analog circuits and/or digital blocks to understand their main functionalities.
• Strong communication and teamwork skills.

We are committed to building an inclusive work environment and do not tolerate racism, discrimination, or harassment of any kind.