SoC Physical Design Engineer — Hybrid Work, Cutting-Edge Nodes

pNokia in Italy seeks a SoC Physical Design Engineer in Catania to advance PD for Optical Network ASICs across 3/5/7nm nodes. You will floorplan, place and route, and manage power/clock distribution, while driving RTL-to-GDSII flows. /ppYou will verify timing at block and chip level, collaborate with logic designers, and develop PD methodologies with automation scripts for Synthesis to GDSII. Hybrid work available. /p #J-18808-Ljbffr